Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines and their drains are coupled to column bit lines. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. The row of selected memory cells then place their data values on the column bit lines by flowing different currents depending on if a particular cell is in a programmed state or an erased state.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line.
The NAND architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. A high bias voltage is applied to a select gate drain line SG(D). In addition, the word lines coupled to the gates of the unselected memory cells of each group are driven to operate the unselected memory cells of each group as pass transistors so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled group, restricted only by the selected memory cells of each group. This places the current encoded data values of the row of selected memory cells on the column bit lines.
FIG. 1 illustrates voltages at various times during typical prior art NAND verify and read operations. Between times T1 and T3, the select gate source SG(S) line is biased with 4.5V. Also during this time, the unselected wordlines are biased with the same voltage. In this example, only WL0 is shown. The selected wordlines are typically between 0V and 0.2V.
Between times T3 and T4 the SG(D) line is biased with 4.5V until the bitline discharges at time T5. The 4.5V bias is removed from all of the lines at time T6.
One problem that might occur with NAND arrays, however, is illustrated in FIG. 1. Due to the small geometry of the NAND architecture, WL0 and SG(D) are capacitively coupled. Similarly, WL32 and SG(S) are capacitively coupled. When the 4.5V bias is applied to the SG(D) line, WL0 also increases by 1.0–1.5V above the 0.2V already on the line. This has the potential to cause read errors since the cells on WL0 are turned on when they are not supposed to be selected.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method for reading NAND memory cells.